The disclosure relates generally to a testing mechanism for a proximity fail probability of defects across integrated chips.
In general, conventional mechanisms that test integrated chips can find defects within the tested chips. These defects can be repaired with redundant elements or can be removed by taking an associated circuit block of the integrated chip off-line. Repair actions may cause the surrounding circuitry, which is still expected to function, to be suspect because of proximity to defects.
In addition, the conventional mechanisms that test integrated chips do not leverage fail diagnostic data to predict undetected fail locations or locations likely to fail due to reliability aging. That is, while defects can be associated with a fail prediction probability, the defects do not guarantee a fail. In turn, the conventional mechanisms only utilize high level sort level details (i.e. ‘nearest neighbor’ sorting) or maverick limits (i.e. excessive array repairs) to resolve defects on the integrated chips, both of which are non-optimal.